1. Field of the Invention
The present invention relates to a semiconductor device having an SOI (Silicon On Insulator) structure and a method of manufacturing the same, and more particularly to a semiconductor device having an isolation insulating film (hereinafter, referred to as a PTI (Partial Trench Isolation) which does not reach a buried oxide film and a method of manufacturing the same.
2. Description of the Background Art
A semiconductor device having an SOI (Silicon On Insulator) structure consisting of a semiconductor substrate, a buried oxide film and a semiconductor layer has no possibility of causing a latch up even if a COMS transistor is formed since an active region is surrounded by the buried oxide film and a device isolation (hereinafter, referred to as FTI (Full Trench Isolation) which reach the buried oxide film). Further, the semiconductor device of SOI structure, in which a transistor is formed on the think semiconductor layer, has a smaller junction capacitance and allows a faster operation with lower power consumption as compared with a semiconductor device in which a transistor is formed directly on a surface of the semiconductor substrate. Therefore, it is recently expected that the semiconductor device of SOI structure should be applied to an LSI for portable device.
Unlike a transistor formed directly on the semiconductor substrate, however, the semiconductor device of SOI structure in the background art has various problems caused by the floating-body effect since the semiconductor layer is electrically isolated from the semiconductor substrate by the buried oxide film. For example, a kink in operation characteristics is caused and the drain breakdown voltage is deteriorated by carriers (positive hole in an NMOS and electrons in a pMOS) which are generated through impact ionization phenomenon in the active region and accumulated inside the semiconductor layer in a lower portion of a channel formation region, and frequency dependency of delay time is caused by instability of a potential in a channel region. To solve these problems, it is effective to fix the potential in the channel formation region. Japanese Patent Application Laid Open Gazette No. 58-124243 discloses a semiconductor device in which the potential is fixed in the channel formation region.
Recently, in order to collectively fix the potentials in the channel formation regions of a plurality of transistors of the same conductivity type, instead of fixing the potential in the channel formation region of each transistor, an isolation is performed by using the PTI for downsizing, and such a structure is disclosed in IEEE International SOI Conference, October 1999 pp. 131 to 132, and the like.
FIG. 22 is a cross section showing a semiconductor device in the background art. The semiconductor device of FIG. 22 comprises a semiconductor substrate 101, a buried oxide film 102, a p-type semiconductor layer 103, an isolation oxide film 104, a gate insulating film 105, a gate electrode 106, n-type source/drain regions 107 and 108, a sidewall insulating film 109, a wire 1010, an interlayer insulating film 1011, a p-type impurity region 1012 and a contact hole 1013. Further, the p-type semiconductor layer 103 below the isolation oxide film 104 is particularly represented as 103a. As shown in FIG. 22, in the case of a PTI, the isolation insulating films 104 between adjacent two transistors and between the p-type impurity region 1012 and the transistor do not reach the buried oxide film 102 and channel formation regions of the two transistors are connected to the p-type impurity region 1012 through the p-type semiconductor layer 103a and the wire 1010 to fix potentials of the channel formation regions in a plurality of transistors of the same conductivity type is connected to the p-type impurity region 1012. The p-type impurity region 1012 has a low resistance, containing an impurity which has a concentration higher than that of the p-type semiconductor layer 103.
Further, for downsizing, the wire 1010 is so formed as to extend onto over a surface of the isolation oxide film 104 (hereinafter, such a structure will be referred to as “borderless contact structure”), to improve the element density.
FIG. 23 is a cross section showing another semiconductor device in the background art. Referring to FIG. 23, the wires 1010 connected to the source/drain regions 107 and 108 are so formed as to extend onto over the surface of the isolation oxide film 104.
Even a semiconductor device having the isolation insulating film of PTI structure to fix the potential of the channel formation region, however, has a problem of causing the floating-body effect since the semiconductor layer below the PTI is thin (up to 50 nm). When the semiconductor layer below the PTI is thin, the resistance between the wire and the transistor becomes higher as goes further away from the wire which fixes the potential of the channel formation region, to badly affect the characteristics of the transistor. Further, there arises a variation in resistance of the channel formation regions in the transistors depending on the distance from the wire which fixes the potential of the channel formation region, which disadvantageously causes a variation in element characteristics.
Furthermore, when it is intended that the element density should be improved by using the borderless contact structure, there is possibility that the isolation oxide film 104 should be also etched when the contact hole 1013 is formed in the interlayer insulating film 1011 since the isolation oxide film 104 and the interlayer insulating film 1011 consisting of a TEOS (tetraethyl orthosilicate) oxide film and the like are of the same quality.
FIG. 24 is a cross section showing a semiconductor device in the background art. As shown in FIG. 24, when the isolation oxide film 104 is etched, the distance from a pn junction between the p-type semiconductor layer 103a below the isolation oxide film 104 and the source region or drain region 107 or 108 to the wire 1010 becomes shorter, to cause an increase injunction leak current.